1. Field of the Invention
This invention relates to integrated injection logic circuits, referred to generally as I.sup.2 L circuits.
Integrated injection logic circuits are described in U.S. Pat. Nos. 4,056,810 and 4,078,208 and for a further description of the mechanism by which such current injection integrated circuits operate and the advantages inherent in the structures, reference is invited to "Philips Technical Review," Volume 33, 1973, No. 3, pages 76 to 85.
2. Description of the Prior Art
Logic circuits employing threshold functions are generally known. Threshold functions generally encompass digital signals which include more levels than the two levels of conventional binary signals. In particular, threshold logic is a digital system in which the output from a gate is determined by an algebraic sum of the weighted inputs, that is, the output state (0 or 1) Q is determined by ##EQU1## where W.sub.m is the numerical weight of the m.sup.th input (where for the purpose of calculation W.sub.m is considered to be restricted to positive or negative integer values),
X.sub.m is the m.sup.th input variable (0 or 1), and, PA1 n is the total number of inputs.
The actual point at which Q changes from 0 to 1 is set by the gate threshold W.sub.t, that is ##EQU2## If for the purpose of calculation W.sub.t is restricted to positive or negative integer plus one-half values no ambiguity arises in these equations.
Thus a single threshold logic gate can be used for deciding whether or not at least x out of y inputs are ON (x&lt;y). Also by the use of the weighting of inputs it is possible to implement Boolean functions such as A+B.multidot.C with a single gate. This is to be compared with normal Boolean logic systems where a gate with a certain number of inputs can perform one only of two functions (and their complements), namely (a) the AND function where all inputs are ON, and (b) the OR function where at least one input is ON.
As an example of the use of a threshold logic gate there is quoted the case where there are three input variables A, B and C respectively having weights W.sub.A =2, W.sub.B =1, W.sub.C =1 and the gate has a threshold weight W.sub.t =11/2. In this case ##EQU3## W.sub.m X.sub.m &gt;W.sub.t, i.e. Q=1, if A=1 or B=C=1 or A=B=C=1. Such a gate therefore detects the state A+(B.multidot.C) where + and .multidot. respectively refer to the Boolean OR and AND connectives. If the threshold weight W.sub.t =21/2 then the state detected is A.multidot.(B+C). For a full description of threshold logic reference is invited to the book by S. L. Hurst entitled "Threshold Logic" (M&B Monograph EE/l 1971).
In U.S. Pat. No. 4,081,822 there are described integrated injection logic circuits having threshold functions. In these circuits multiple-collector input transistors are employed to switch states under control of binary input signals. The collectors of the input transistors are connected to the bases of one or more output transistors which have different threshold weights determined by different levels of injection current. The ON or OFF state of each output transistor is controlled by its threshold weight and by the state of one or more input transistors to which it is connected. The injection current is conducted into the output transistor base or into an input transistor collector depending upon whether the input transistor is OFF or ON. Single weighted output transistors are in the OFF state when at least a single connected input transistor is in the ON state. Double weighted output transistors are in the OFF state only when at least two connected input transistors are in the ON state and so on.
In these circuits the threshold function is built up from a plurality of interconnected transistors and implementation of certain functions requires long series connections of transistors resulting in some instances in long propogation delay times. Furthermore in this system the basic gate, namely the basic I.sup.2 L transistor gate, is not a full threshold gate, the threshold gate having to be built up from a series of the basic I.sup.2 L transistor gates. Also in this system it is not readily possible to implement logic inputs with negative weightings.